As electronic products become smaller, for the large scale integration (LSI) circuitry and very large scale integration (VLSI) circuitry used in many consumer electronics such as laptops, tablets, smart phones, and digital cameras, there are increasing higher requirements on the feature sizes of semiconductor chips. Thus, the semiconductor packaging structures also need to become smaller and smaller, thinner and thinner.
FIG. 1 shows a cross-sectional view of an existing packaging structure. As shown in FIG. 1, the packaging structure includes: a packaging substrate 10, and a chip 20 disposed on the packaging substrate 10. A first surface 11 of the packaging substrate 10 is disposed opposite to a second surface 21 of the chip 20.
The packaging structure also includes a plurality of solder balls 22 formed on the second surface 21 of the chip 20. The solder balls 22 are electrically connected to the circuits (not shown) in the chip 20, and also connected to conductive terminals 15 on the first surface 11 of the packaging substrate 10. Thus, the circuitry in the chip 20 is connected to external circuitry through the solder balls 22 and the conductive terminals 15.
Further, the packaging structure includes an underfill 30 filled between the chip 20 and the packaging substrate 10, and a resin packaging material 40 covering the chip 20 and the surface of the packaging substrate 10. Because the distance between the chip 20 and the packaging substrate 10 is very small, this distance equals to the height of the solder balls 22. Thus, when the resin packaging material 40 is formed on the chip 20 and the surface of the packaging substrate 10, the resin packaging material 40 would not fill into the gap between the chip 20 and the packaging substrate 10.
Therefore, internal voids can form, which may cause charge and moisture to accumulate and corrosion in the chip and the packaging substrate. Even if the gap between the chip 20 and the packaging substrate 10 is first filled with the underfill 30 and then the chip 20 and the surface of the packaging substrate 10 are covered by the resin packaging material 40, because the gap is small, voids may still be formed between the chip 20 and the packaging substrate 10, impacting the stability and reliability of the chip 20.
The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.